View source for Dream Turbo Card by pear

[[File:DTCdesign.jpg|thumb|400px|Dream Turbo Card (design stage)]]
=Brief information=
Dream Turbo Card (DTC) is an internal card with RAM & FlashROM memory, real-time clock (RTC) and switched clock generators for the system and EXDOS.

=Specification=
* 1 MB SRAM, optionally 2 MB, in banks of 64KB,
* 512 KB FlashROM, 8 banks of 64 KB with the option of individual switching off, EXOS in bank 7 (always on),
* RTC clock,
* NVRAM (battery backup),
* two-channel synchronized clock signal generator:
** system clock 4/8/12/16/20 MHz (2/4/6/8/10 MHz Z80 CPU),
** EXDOS clock 8/9.6/10/12/13.33/16 MHz
* LCD or OLED display (2x16 chars),
* RGB LED to signal by colors the selected CPU clock:
** 2MHz <span style="color: #08f">'''blue'''</span>,
** 4MHz <span style="color: #080">'''green'''</span>,
** 6MHz <span style="color: #ff0">'''yellow'''</span>,
** 8MHz <span style="color: #f60">'''orange'''</span>,
** 10MHz <span style="color: #f00">'''red'''</span>,
* optional temperature sensor for NICK,
* configured by rotary encoder or by software.

=Features=
==Card access==
{|class="wikitable"
!I/O address
!Direction
!Content
|-
|rowspan=2|0x7E||write||NVRAM address select
|-
|read||card [[Dream Turbo Card by pear#Status register|status register]]
|-
|rowspan=2|0x7F||write||rowspan=2|NVRAM data
|-
|read
|}

==Status register==
{|class="wikitable"
!Bit
!Name
!Content
|-
!scope="row"|0
|style="text-align:center"|EP RFSH||microcontroller saved new data into the NVRAM memory (EP should be read them, the read from NVRAM data port resets this bit)
|-
!scope="row"|1
|style="text-align:center"|CLK Sys Ready||system clock synchronized to the current setting
|-
!scope="row"|2
|style="text-align:center"|CLK EXDOS Ready||EXDOS clock synchronized to the current setting
|-
!scope="row"|3
|style="text-align:center"|RTC RQ||card microcontroller requests access to NVRAM memory
|-
!scope="row"|4
|style="text-align:center"|RTC RFSH||EP saved new data into the NVRAM memory (the read by card microcontroller resets this bit)
|-
!scope="row"|5
|style="text-align:center"|reserved||for now always '0'
|-
!scope="row"|6
|style="text-align:center"|S0||microcontroller status bit 0 (1 = temperature reading completed)
|-
!scope="row"|7
|style="text-align:center"|S1||microcontroller status bit 1 (not used yet)
|}

==Config registers==
{|class="wikitable"
!colspan=2|Address
!colspan=8|Bits
!rowspan=2|Content
|-
!scope="row"|NVRAM||CPLD||style="width: 50px"|7||style="width: 50px"|6||style="width: 50px"|5||style="width: 50px"|4||style="width: 50px"|3||style="width: 50px"|2||style="width: 50px"|1||style="width: 50px"|0
|-
|0x7F<sup> *)</sup>||style="text-align:center"|NA||colspan=8 style="text-align:center"|Device ID
|style="text-align:center"|Dream Turbo Card ID is 44h
|-
|0x7E<sup> *)</sup>||style="text-align:center"|NA||colspan=4 style="text-align:center"|Hw batch no.||colspan=4 style="text-align:center"|Hw serial no.
|style="text-align:center"|Hardware serial number
|-
|0x7D<sup> *)</sup>||style="text-align:center"|NA||colspan=4 style="text-align:center"|Hw ver. mj.||colspan=4 style="text-align:center"|Hw ver. mn.
|style="text-align:center"|Hardware version (major.minor)
|-
|0x7C<sup> *)</sup>||style="text-align:center"|NA||colspan=4 style="text-align:center"|Fw ver. mj.||colspan=4 style="text-align:center"|Fw ver. mn.
|style="text-align:center"|Firmware version (major.minor)
|-
|0x7B<sup> *)</sup>||style="text-align:center"|NA||style="text-align:center"|DSP
|style="text-align:center"|LS||style="text-align:center"|RAM2||style="text-align:center"|uC
|colspan=2 style="text-align:center"|TEMP||colspan=2 style="text-align:center"|Flash||style="text-align:center"|Features (below)
|-
|0x7A||style="text-align:center"|3
|colspan=2 style="text-align:center"|[[Dream Turbo Card by pear#Memory map|Memory mode]]
|colspan=3 style="text-align:center"|EXDOS [[Dream Turbo Card by pear#Clock selection|clock select]]
|colspan=3 style="text-align:center"|System [[Dream Turbo Card by pear#Clock selection|clock select]]
|style="text-align:center"|Memory bank mode, selection of clocks (below)
|-
|0x79||style="text-align:center"|2||style="text-align:center"|[[Dream Turbo Card by pear#Minimum value of system clock in "linked mode"|CLK link]]||style="text-align:center"|Flash.6
|style="text-align:center"|Flash.5||style="text-align:center"|Flash.4||style="text-align:center"|Flash.3
|style="text-align:center"|Flash.2||style="text-align:center"|Flash.1||style="text-align:center"|Flash.0
|style="text-align:center"|Disabling flash memory banks, bit N=1 Flash bank N disable
|-
|0x78<sup> *)</sup>||style="text-align:center"|1||style="text-align:center"|S1||style="text-align:center"|S0
|colspan=6 style="text-align:center"|LCD bias
|style="text-align:center"|uC status bits & LCD contrast
|-
|0x77<sup> *)</sup>||style="text-align:center"|0||colspan=2 style="text-align:center"|LCD backlight||colspan=2 style="text-align:center"|LED blue
|colspan=2 style="text-align:center"|LED green||colspan=2 style="text-align:center"|LED red
|style="text-align:center"|LCD backlight and RGB LED control
|-
|0x76<sup> *)</sup>||style="text-align:center"|NA||colspan=8 style="text-align:center"|Current temperature
|style="text-align:center"|Current NICK temperature
|-
|0x75||style="text-align:center"|NA||colspan=8 style="text-align:center"|Temperature limit
|style="text-align:center"|NICK temperature level for the alarm (0 = alarm off)
|}
<sup> *)</sup> read-only, data will be always overwritten by the card microcontroller, 

{|class="wikitable"
!Feature
!Description
!Value
!Type
|-
|rowspan=4 style="text-align:center"|Flash||rowspan=4 style="text-align:left"|Flash chip type
|style="text-align:center"|00||Microchip SST39SF040
|-
|style="text-align:center"|01||.
|-
|style="text-align:center"|10||.
|-
|style="text-align:center"|11||.
|-
|rowspan=4 style="text-align:center"|TEMP||rowspan=4 style="text-align:left"|temperature sensor type
|style="text-align:center"|00||none
|-
|style="text-align:center"|01||Dallas DS18B20
|-
|style="text-align:center"|10||Analog Devices TMP03/04
|-
|style="text-align:center"|11||Analog Devices TMP05/06
|-
|rowspan=2 style="text-align:center"|uC||rowspan=2 style="text-align:left"|microcontroller type
|style="text-align:center"|0||MCS51
|-
|style="text-align:center"|1||AVR
|-
|rowspan=2 style="text-align:center"|RAM2||rowspan=2 style="text-align:left"|RAM capacity
|style="text-align:center"|0||1 MB
|-
|style="text-align:center"|1||2 MB
|-
|rowspan=2 style="text-align:center"|LS||rowspan=2 style="text-align:left"|sound transducer
|style="text-align:center"|0||buzzer or none
|-
|style="text-align:center"|1||loudspeaker
|-
|rowspan=2 style="text-align:center"|DSP||rowspan=2 style="text-align:left"|display type
|style="text-align:center"|0||OLED
|-
|style="text-align:center"|1||LCD
|}

==Memory map==

MT is MICROTEAM card.

{|class="wikitable" style="float:left; margin-right: 10px"
!colspan=5|Mode 0 (default)
|-
!scope="row"|BANK||style="width: 70px; text-align:center"|x0-x3||style="width: 70px; text-align:center"|x4-x7||style="width: 70px; text-align:center"|x8-xB||style="width: 70px; text-align:center"|xC-xF
|-
!scope="col"|0x
|style="text-align:center; background-color: #00b0f0"|Flash.7||style="text-align:center; background-color: #ed7d31"|CART
|style="text-align:center; background-color: #cc0099"|EPNET||style="text-align:center; background-color: #cc0099"|EPNET
|-
!scope="col"|1x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|2x
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|3x
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|4x
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|-
!scope="col"|5x
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|-
!scope="col"|6x
|style="text-align:center; background-color: #0070c0"|Flash.0||style="text-align:center; background-color: #0070c0"|Flash.1
|style="text-align:center; background-color: #0070c0"|Flash.2||style="text-align:center; background-color: #0070c0"|Flash.3
|-
!scope="col"|7x
|style="text-align:center; background-color: #0070c0"|Flash.4||style="text-align:center; background-color: #0070c0"|Flash.5
|style="text-align:center; background-color: #0070c0"|Flash.6||style="text-align:center; background-color: #00b050"|RAM1.F
|-
!scope="col"|8x
|style="text-align:center; background-color: #92d050"|RAM2.0||style="text-align:center; background-color: #92d050"|RAM2.1
|style="text-align:center; background-color: #92d050"|RAM2.2||style="text-align:center; background-color: #92d050"|RAM2.3
|-
!scope="col"|9x
|style="text-align:center; background-color: #92d050"|RAM2.4||style="text-align:center; background-color: #92d050"|RAM2.5
|style="text-align:center; background-color: #92d050"|RAM2.6||style="text-align:center; background-color: #92d050"|RAM2.7
|-
!scope="col"|Ax
|style="text-align:center; background-color: #92d050"|RAM2.8||style="text-align:center; background-color: #92d050"|RAM2.9
|style="text-align:center; background-color: #92d050"|RAM2.A||style="text-align:center; background-color: #92d050"|RAM2.B
|-
!scope="col"|Bx
|style="text-align:center; background-color: #92d050"|RAM2.C||style="text-align:center; background-color: #92d050"|RAM2.D
|style="text-align:center; background-color: #92d050"|RAM2.E||style="text-align:center; background-color: #92d050"|RAM2.F
|-
!scope="col"|Cx
|style="text-align:center; background-color: #00b050"|RAM1.0||style="text-align:center; background-color: #00b050"|RAM1.1
|style="text-align:center; background-color: #00b050"|RAM1.2||style="text-align:center; background-color: #00b050"|RAM1.3
|-
!scope="col"|Dx
|style="text-align:center; background-color: #00b050"|RAM1.4||style="text-align:center; background-color: #00b050"|RAM1.5
|style="text-align:center; background-color: #00b050"|RAM1.6||style="text-align:center; background-color: #00b050"|RAM1.7
|-
!scope="col"|Ex
|style="text-align:center; background-color: #00b050"|RAM1.8||style="text-align:center; background-color: #00b050"|RAM1.9
|style="text-align:center; background-color: #00b050"|RAM1.A||style="text-align:center; background-color: #00b050"|RAM1.B
|-
!scope="col"|Fx
|style="text-align:center; background-color: #00b050"|RAM1.C||style="text-align:center; background-color: #00b050"|RAM1.D
|style="text-align:center; background-color: #00b050"|RAM1.E||style="text-align:center; background-color: #ff0000"|VRAM
|}
{|class="wikitable" style="float:left; margin-right: 10px"
!colspan=5|Mode 1 (no RAM2)
|-
!scope="row"|BANK||style="width: 70px; text-align:center"|x0-x3||style="width: 70px; text-align:center"|x4-x7||style="width: 70px; text-align:center"|x8-xB||style="width: 70px; text-align:center"|xC-xF
|-
!scope="col"|0x
|style="text-align:center; background-color: #00b0f0"|Flash.7||style="text-align:center; background-color: #ed7d31"|CART
|style="text-align:center; background-color: #cc0099"|EPNET||style="text-align:center; background-color: #cc0099"|EPNET
|-
!scope="col"|1x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|2x
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|3x
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|4x
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|-
!scope="col"|5x
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|-
!scope="col"|6x
|style="text-align:center; background-color: #0070c0"|Flash.0||style="text-align:center; background-color: #0070c0"|Flash.1
|style="text-align:center; background-color: #0070c0"|Flash.2||style="text-align:center; background-color: #0070c0"|Flash.3
|-
!scope="col"|7x
|style="text-align:center; background-color: #0070c0"|Flash.4||style="text-align:center; background-color: #0070c0"|Flash.5
|style="text-align:center; background-color: #0070c0"|Flash.6||style="text-align:center; background-color: #00b050"|RAM1.F
|-
!scope="col"|8x
|style="text-align:center"|not used||style="text-align:center"|not used
|style="text-align:center"|not used||style="text-align:center"|not used
|-
!scope="col"|9x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|Ax
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|Bx
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|Cx
|style="text-align:center; background-color: #00b050"|RAM1.0||style="text-align:center; background-color: #00b050"|RAM1.1
|style="text-align:center; background-color: #00b050"|RAM1.2||style="text-align:center; background-color: #00b050"|RAM1.3
|-
!scope="col"|Dx
|style="text-align:center; background-color: #00b050"|RAM1.4||style="text-align:center; background-color: #00b050"|RAM1.5
|style="text-align:center; background-color: #00b050"|RAM1.6||style="text-align:center; background-color: #00b050"|RAM1.7
|-
!scope="col"|Ex
|style="text-align:center; background-color: #00b050"|RAM1.8||style="text-align:center; background-color: #00b050"|RAM1.9
|style="text-align:center; background-color: #00b050"|RAM1.A||style="text-align:center; background-color: #00b050"|RAM1.B
|-
!scope="col"|Fx
|style="text-align:center; background-color: #00b050"|RAM1.C||style="text-align:center; background-color: #00b050"|RAM1.D
|style="text-align:center; background-color: #00b050"|RAM1.E||style="text-align:center; background-color: #ff0000"|VRAM
|}
{|class="wikitable" style="float:left; margin-right: 10px"
!colspan=5|Mode 2 (no Flash)
|-
!scope="row"|BANK||style="width: 70px; text-align:center"|x0-x3||style="width: 70px; text-align:center"|x4-x7||style="width: 70px; text-align:center"|x8-xB||style="width: 70px; text-align:center"|xC-xF
|-
!scope="col"|0x
|style="text-align:center; background-color: #00b0f0"|Flash.7||style="text-align:center; background-color: #ed7d31"|CART
|style="text-align:center; background-color: #cc0099"|EPNET||style="text-align:center; background-color: #cc0099"|EPNET
|-
!scope="col"|1x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|2x
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|3x
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|4x
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|-
!scope="col"|5x
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|-
!scope="col"|6x
|style="text-align:center; background-color: #92d050"|RAM2.8||style="text-align:center; background-color: #92d050"|RAM2.9
|style="text-align:center; background-color: #92d050"|RAM2.A||style="text-align:center; background-color: #92d050"|RAM2.B
|-
!scope="col"|7x
|style="text-align:center; background-color: #92d050"|RAM2.C||style="text-align:center; background-color: #92d050"|RAM2.D
|style="text-align:center; background-color: #92d050"|RAM2.E||style="text-align:center; background-color: #00b050"|RAM1.F
|-
!scope="col"|8x
|style="text-align:center; background-color: #92d050"|RAM2.0||style="text-align:center; background-color: #92d050"|RAM2.1
|style="text-align:center; background-color: #92d050"|RAM2.2||style="text-align:center; background-color: #92d050"|RAM2.3
|-
!scope="col"|9x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|Ax
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|Bx
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|Cx
|style="text-align:center; background-color: #00b050"|RAM1.0||style="text-align:center; background-color: #00b050"|RAM1.1
|style="text-align:center; background-color: #00b050"|RAM1.2||style="text-align:center; background-color: #00b050"|RAM1.3
|-
!scope="col"|Dx
|style="text-align:center; background-color: #00b050"|RAM1.4||style="text-align:center; background-color: #00b050"|RAM1.5
|style="text-align:center; background-color: #00b050"|RAM1.6||style="text-align:center; background-color: #00b050"|RAM1.7
|-
!scope="col"|Ex
|style="text-align:center; background-color: #00b050"|RAM1.8||style="text-align:center; background-color: #00b050"|RAM1.9
|style="text-align:center; background-color: #00b050"|RAM1.A||style="text-align:center; background-color: #00b050"|RAM1.B
|-
!scope="col"|Fx
|style="text-align:center; background-color: #00b050"|RAM1.C||style="text-align:center; background-color: #00b050"|RAM1.D
|style="text-align:center; background-color: #00b050"|RAM1.E||style="text-align:center; background-color: #ff0000"|VRAM
|}
{|class="wikitable" style="float:left; margin-right: 10px; clear: right"
!colspan=5|Mode 3 (no Flash & RAM2)
|-
!scope="row"|BANK||style="width: 70px; text-align:center"|x0-x3||style="width: 70px; text-align:center"|x4-x7||style="width: 70px; text-align:center"|x8-xB||style="width: 70px; text-align:center"|xC-xF
|-
!scope="col"|0x
|style="text-align:center; background-color: #00b0f0"|Flash.7||style="text-align:center; background-color: #ed7d31"|CART
|style="text-align:center; background-color: #cc0099"|EPNET||style="text-align:center; background-color: #cc0099"|EPNET
|-
!scope="col"|1x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|2x
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|3x
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|4x
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|style="text-align:center; background-color: #ffc000"|MT DRAM1||style="text-align:center; background-color: #ffc000"|MT DRAM1
|-
!scope="col"|5x
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|style="text-align:center; background-color: #ffff00"|MT DRAM2||style="text-align:center; background-color: #ffff00"|MT DRAM2
|-
!scope="col"|6x
|style="text-align:center"|not used||style="text-align:center"|not used
|style="text-align:center"|not used||style="text-align:center"|not used
|-
!scope="col"|7x
|style="text-align:center"|not used||style="text-align:center"|not used
|style="text-align:center"|not used||style="text-align:center; background-color: #00b050"|RAM1.F
|-
!scope="col"|8x
|style="text-align:center"|not used||style="text-align:center"|not used
|style="text-align:center"|not used||style="text-align:center"|not used
|-
!scope="col"|9x
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|style="text-align:center; background-color: #ffccff"|MT SRAM1||style="text-align:center; background-color: #ffccff"|MT SRAM1
|-
!scope="col"|Ax
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|style="text-align:center; background-color: #ff99cc"|MT Flash||style="text-align:center; background-color: #ff99cc"|MT Flash
|-
!scope="col"|Bx
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|style="text-align:center; background-color: #ff6699"|MT SRAM2||style="text-align:center; background-color: #ff6699"|MT SRAM2
|-
!scope="col"|Cx
|style="text-align:center; background-color: #00b050"|RAM1.0||style="text-align:center; background-color: #00b050"|RAM1.1
|style="text-align:center; background-color: #00b050"|RAM1.2||style="text-align:center; background-color: #00b050"|RAM1.3
|-
!scope="col"|Dx
|style="text-align:center; background-color: #00b050"|RAM1.4||style="text-align:center; background-color: #00b050"|RAM1.5
|style="text-align:center; background-color: #00b050"|RAM1.6||style="text-align:center; background-color: #00b050"|RAM1.7
|-
!scope="col"|Ex
|style="text-align:center; background-color: #00b050"|RAM1.8||style="text-align:center; background-color: #00b050"|RAM1.9
|style="text-align:center; background-color: #00b050"|RAM1.A||style="text-align:center; background-color: #00b050"|RAM1.B
|-
!scope="col"|Fx
|style="text-align:center; background-color: #00b050"|RAM1.C||style="text-align:center; background-color: #00b050"|RAM1.D
|style="text-align:center; background-color: #00b050"|RAM1.E||style="text-align:center; background-color: #ff0000"|VRAM
|}
<div style="clear: left"> </div>

==Clock selection==
{|class="wikitable"
!SELECT
!System clock
!CPU clock
!EXDOS clock
|-
!scope="col" style="text-align:center"|0
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz||style="text-align:center"|8 MHz
|-
!scope="col" style="text-align:center"|1
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz||style="text-align:center"|9.6 MHz
|-
!scope="col" style="text-align:center"|2
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz||style="text-align:center"|10 MHz
|-
!scope="col" style="text-align:center"|3
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz||style="text-align:center"|12 MHz
|-
!scope="col" style="text-align:center"|4
|style="text-align:center"|4 MHz||style="text-align:center; background-color: #08f"|2 MHz||style="text-align:center"|13.33 MHz
|-
!scope="col" style="text-align:center"|5
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz||style="text-align:center"|16 MHz
|-
!scope="col" style="text-align:center"|6
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz||style="text-align:center"|8 MHz
|-
!scope="col" style="text-align:center"|7
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz||style="text-align:center"|8 MHz
|}

===Minimum value of system clock in "linked mode"===
When we raise the EXDOS clock frequency, the data from the FDC controller will be sent faster.<br>
In some cases, the processor clocked by a lower frequency may not be able to process transmitted data.<br>
To prevent this situation, it is possible to activate the "linking" mode of clock signals.<br>
In this mode the card's microcontroller will ensure that the processor's clock frequency is not less than the minimum frequency at which the processor is able to keep pace with data from the FDC controller.
{|class="wikitable"
!Selected system clock
!colspan=2|4 MHz
!colspan=2|8 MHz
!colspan=2|12 MHz
!colspan=2|16 MHz
!colspan=2|20 MHz
|-
!Selected EXDOS clock
!colspan=10|Actual frequency (System/CPU)
|-
!8 MHz
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz
|-
!9.6 MHz
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz
|-
!10 MHz
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz
|style="text-align:center"|8 MHz||style="text-align:center; background-color: #080"|4 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz
|-
!12 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz
|-
!13.33 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|12 MHz||style="text-align:center; background-color: #ff0"|6 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz
|-
!16 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|16 MHz||style="text-align:center; background-color: #f60"|8 MHz
|style="text-align:center"|20 MHz||style="text-align:center; background-color: #f00"|10 MHz
|}

=How to install=
DTC is a complex interface. The installation requires interference with the computer.<br>
The author has made every effort to make the interface as reliable and safe to use as possible. However,
<pre style="color: red; font-size: 1.7em; font-family: calibri">You make any modifications inside of your equipment at your own risk !</pre>
==What you need==
* Dream Turbo Card
* L-connector
* new Z80 processor suitable for work at clock speeds of at least 10 MHz (eg. Z84C0010P, Z84C0020P)

==Enterprise mainboard preparation==
* desolder and remove  internal 64KB RAM memory module (Enterprise 128 only)
* desolder the Z80 processor
* 
==Installation of the L-connector==
* 
==First start==
*

=Links=
Thread on the Enterprise Forever forum [https://enterpriseforever.com/hardware/6mhz-and-more/ 6Mhz and more...]

=Manual in other languages=
[[DreamTurboCard_(Spanish)|Español]]

[[DreamTurboCard_(Polski)|Polski]]

[[DreamTurboCard_(Deutsch)|Deutsch]]

[[DreamTurboCard_(Magyar)|Magyar]]